The present invention relates to display-integrated type tablet devices for use in personal computers, word processors and the like.
As means for inputting handwritten characters and graphics into a computer, a word processor, or the like, there have been provided, in practical use, display-integrated type tablet devices in which, for example, an LCD (liquid crystal display) and an electrostatic induction tablet are stacked on each other so that characters and graphics can be inputted into the electrostatic induction tablet at a feeling that we write them on paper with some writing instrument. However, this type of display-integrated type tablet device has different coefficients of reflectance and transmittance between its portions where electrode exist and those where not, such that electrodes can be seen in a lattice form on the display screen, causing some deterioration in the display quality of the LCD.
In view of this problem, the present inventor has recently proposed a display-integrated type tablet device, as shown in FIG. 1, which has overcome such defects as described above, though it is not laid-opened and not known by the other.
This display-integrated type tablet device has one which serves as both the display electrode of an LCD and the position detection electrode of an electrostatic capacity type tablet device. In the tablet device, there are provided a coordinate detection period, during which specified coordinates on the tablet are detected, and a display period, during which an image is displayed, into a one-frame period, as shown in FIG. 2, whereby coordinate detection and image display are carried out by time sharing.
Referring to FIG. 1, a liquid crystal panel 1 is so constructed that liquid crystals are sandwiched between common electrodes Y.sub.1 -Y.sub.n (hereinafter, an arbitrary common electrode will be represented as Y) and segment electrodes X.sub.1 -X.sub.m (hereinafter, an arbitrary segment electrode will be represented as X), each electrode group being arranged so as to cross at right angles, wherein pixels are formed one for each region at which a common electrode Y and a segment electrode X cross each other. As a result, the liquid crystal panel 1 has n by m dot pixels arranged therein in a matrix form.
This display-integrated type tablet device has some advantages as compared with the above-described one, in which an electrostatic capacity type tablet is stacked on an LCD display, besides the advantage that the lattice-like electrode pattern has been eliminated so that the display becomes easy to view: that is, it can be easily reduced in cost as well as in size and weight, because electrodes and drive circuits are shared between the LCD and the electrostatic capacity type tablet.
The display-integrated type tablet device operates in the following manner. A common drive circuit 2 for driving the common electrode Y and a segment drive circuit 3 for driving the segment electrode X are connected to a display control circuit 5 and a detection control circuit 6 via a switching circuit 4. The switching circuit 4, being controlled by a control circuit 7, delivers an output signal from the display control circuit 5 to the common drive circuit 2 and the segment drive circuit 3 during a display period while it delivers an output from the detection control circuit 6 to the common drive circuit 2 and the segment drive circuit 3 during a coordinate detection period.
It is to be noted that although in FIG. 1 the switching circuit 4, the display control circuit 5, the detection control circuit 6, and the control circuit 7 are diagramed as divided into blocks, yet they are practically LSI-integrated such that they cannot so strictly be divided into such blocks from the viewpoint of form.
In the display period, shift data s is outputted from a shift data output terminal S of the display control circuit 5, an inversion signal fr is outputted from an inversion signal output terminal FR, a clock signal cp1 is outputted from a clock output terminal CP1, a clock signal cp2 is outputted from a clock output terminal CP2, and display data D.sub.0 -D.sub.3 are outputted form data output terminals D0-D3.
The clock signal cp1, a clock signal that cycles at the period during which one-line pixels are displayed, is inputted as a clock signal cp1o into both a clock input terminal YCK of the common drive circuit 2 and a latch pulse input terminal XLP of the segment drive circuit 3 via an output terminal CP1O of the switching circuit 4. Also, the shift data s, a pulse signal for assigning each common electrode Y, is inputted as a shift data so into a shift data input terminal DIO1 of the common drive circuit 2 via an output terminal SO of the switching circuit 4 in synchronization with the clock signal cp1o.
When the shift data so is inputted into the common drive circuit 2, pulse position of the shift data so is shifted by a shift register, and a common electrode drive signal is outputted from output terminals 01-0n of the common drive circuit 2 corresponding to the shift positions to common electrodes Y.sub.1 -Y.sub.n. This common electrode drive signal is generated depending on bias power supplies V.sub.0 -V.sub.5 fed from a d.c. power supply circuit 12.
The clock signal cp2, a clock signal that cycles at a period resulting from dividing a few times the period during which one-line pixels are displayed, is inputted as a clock signal cp2o into a clock input terminal XCK of the segment drive circuit 3 via an output terminal CP20 of the switching circuit 4.
The display data D.sub.0 -D.sub.3 are inputted into input terminals XD0-XD3 of the segment drive circuit 3 via output terminals D0O-D3O of the switching circuit 4 as display data D.sub.0 o-D.sub.3 o, and successively entrapped into a register within the segment drive circuit 3 in synchronization with the clock signal cp2o. When display data corresponding to one-line pixels are all entrapped, the entrapped display data are latched at the timing of the clock signal cp1o to be inputted into the latch pulse input terminal XLP, and segment electrode drive signals respectively corresponding to the display data are outputted from output terminals 01-0m of the segment drive circuit 3 to segment electrodes X.sub.1 -X.sub.m. The segment drive signals are also generated depending on the bias power supplies V.sub.0 -V.sub.5 fed from the d.c. power supply circuit 12.
The inversion signal fr is a signal for preventing any deterioration of the liquid crystals due to electrolysis by periodically inverting the direction in which the voltage is applied to the liquid crystals during the display period, and it is inputted as an inversion signal fro into an inversion signal input terminal YFR of the common drive circuit 2 and an inversion signal input terminal XFR of the segment drive circuit 3 via an inversion signal output terminal FRO of the switching circuit 4.
Thus, the pixel matrix of the liquid crystal panel 1 is driven according to its line order by operation of the common drive circuit 2 and the segment drive circuit 3, so that an image corresponding to the display data D.sub.0 -D.sub.3 is displayed onto the liquid crystal panel 1.
During the coordinate detection period, on the other hand, shift data sd is outputted from a shift data output terminal Sd of the detection control circuit 6, an inversion signal frd is outputted from an inversion signal output terminal FRd, a clock signal cp1d is outputted from a clock output terminal CP1d, a clock signal cp2d is outputted from a clock output terminal CP2d, and drive data D.sub.0 d-D.sub.3 d are outputted from data output terminals D.sub.0 d-D.sub.3 d.
The clock signal cp1d, a clock signal that cycles at the scanning period during which one-line common electrodes are scanned, is inputted as a clock signal cp1o into the clock input terminal YCK of the common drive circuit 2 and the latch pulse input terminal XLP of the segment drive circuit 3 via an output terminal CP1O of the switching circuit 4. The shift data sd, a pulse signal for assigning each common electrode Y, is inputted as shift data so into the shift data input terminal DIO1 of the common drive circuit 2 via the output terminal SO of the switching circuit 4 in synchronization with the clock signal cp1d.
Then, as in the case with the display period, pulse position of the shift data so is shifted by the shift register of the common drive circuit 2, and common electrode scan signals Y.sub.1 -Y.sub.n (hereinafter, an arbitrary common electrode scan signal will be represented as y) are successively outputted from the output terminals 01-0n corresponding to the shift positions to the common electrodes Y.sub.1 -Y.sub.n. This common electrode scan signal y is generated depending on the bias power supplies V.sub.0 -V.sub.5 fed from the d.c. power supply circuit 12.
The clock signal cp2d, a clock signal that cycles at a period resulting from dividing a few times the scan period during which one-line common electrodes Y are scanned, is inputted as a clock signal cp2o into the clock input terminal XCK of the segment drive circuit 3 via the output terminal CP2O of the switching circuit 4.
The drive data D.sub.0 d-D.sub.3 d are inputted as drive data D.sub.0 o-D.sub.3 o into the input terminals XD0-XD3 of the segment drive circuit 3 via output terminals D0O-D3O of the switching circuit 4, and entrapped into the register within the segment drive circuit 3 in synchronization with the clock signal 2o. When one-line drive data are entrapped, the entrapped drive data is latched at the timing of the clock signal cp1o to be inputted into the latch pulse input terminal XLP, while segment electrode scan signals x.sub.1 -x.sub.m (hereinafter, an arbitrary segment electrode scan signal will be represented as x) respectively corresponding to the drive data are outputted from the output terminals 01-0m of the segment drive circuit 3 to the segment electrodes X.sub.1 -X.sub.m. This segment electrode scan signal x is also generated depending on the bias power supplies V.sub.0 -V.sub.5 fed from the d.c. power supply circuit 12.
FIG. 3 is a timing chart of scan signals involved in the coordinate detection period of the above-mentioned display-integrated type tablet device. The coordinate detection period is divided into an x-coordinate detection period and a succeeding y-coordinate detection period, and a segment electrode scan signal x, which is a pulse voltage signal, is successively applied to a segment electrode X during the x-coordinate detection period while a common electrode scan signal y, which is a pulse voltage signal, is successively applied to a common electrode Y during the y-coordinate detection period.
By application of the pulse voltage signals, there is induced a voltage to a specified-coordinate detection pen 8 (hereinafter, simply referred to as detection pen) due to a floating capacity between the segment electrode X or common electrode Y and the tip electrode of the detection pen 8. The induced voltage developed to the detection pen 8 is amplified by an amplifier 9, and inputted into an x-coordinate detection circuit 10 and a y-coordinate detection circuit 11.
The x-coordinate detection circuit 10 and the y-coordinate detection circuit 11 detect the time elapse from when the pulse voltage signal is applied until when the induced voltage reaches its peak value, depending on the output signal from the amplifier 9 and the timing signal from the control circuit 7, thereby detecting the x-coordinate or the y-coordinate, respectively, of the position specified by the detection pen 8.
The above-described display-integrated type tablet device successively and repeatedly selects and displays among the common electrodes Y.sub.1 -Y.sub.n during the display period, thus the duty ratio of display (ratio of a one-line display period to a one-frame display period) being 1/n. Accordingly, when n is small, the duty ratio of display does not become so small and therefore the display contrast does not lower, whereas some high-resolution displays, which may involve a value of n, 480 or more, would cause the display contrast to lower to a disadvantage.
As LCD devices whose duty ratio of display is made larger, there have conventionally been known such LCD devices as shown in FIG. 4 or FIG. 5. In these figures the number of common electrodes Y is assigned 8 for simplicity of explanation.
The LCD device the main part of which is block-diagramed in FIG. 4 is so arranged that there are provided segment electrode of independent groups in equal number and at equal intervals to the upper half 1wU and the lower half 1wL of a display panel 1w, and each electrode group is to be driven by independent segment drive circuits. More specifically, upper segment electrodes X.sub.1 U, . . . , X.sub.m U provided to the upper half 1wU of the display panel 1w (hereinafter, an arbitrary upper segment electrode will be represented as XU) are driven by an upper segment drive circuit 3U. On the other hand, lower segment electrodes X.sub.1 L, . . . , X.sub.m L provided to the lower half 1wL of the display panel 1w (hereinafter, an arbitrary lower segment electrode will be represented as XL) are driven by a lower segment drive circuit 3L.
Meanwhile, upper common electrodes Y.sub.1 -Y.sub.4 belonging to the upper half 1wU of the display panel 1w (hereinafter, an arbitrary upper common electrode will be represented as YU) are driven by an upper common drive circuit 2U. On the other hand, lower common electrodes Y.sub.5 -Y.sub.8 belonging to the lower half 1wL of the display panel 1w (hereinafter, an arbitrary lower common electrode will be represented as YL) are driven by an lower common drive circuit 2L.
The upper half 1wU and the lower half 1wL in the screen of the display panel 1w are each driven by the same manner as with the example of FIG. 1.
More specifically, for the upper half 1wU, the upper common electrodes Y.sub.1 -Y.sub.4 are successively driven from one end to another by the upper common drive circuit 2U while a group of the upper segment electrodes XU are driven by the upper segment drive circuit 3U.
Likewise, for the lower half 1wL, the lower common electrodes Y.sub.5 -Y.sub.8 are successively driven from one end to another by the lower common drive circuit 2L while a group of the lower segment electrodes XL are driven by the lower segment drive circuit 3L.
In so doing, display of the upper half 1wU of the display panel 1w and that of its lower half 1wL are carried out simultaneously in parallel. That is, common electrode pairs, Y.sub.1 and Y.sub.5, Y.sub.2 and Y.sub.6, Y.sub.3 and Y.sub.7, and Y.sub.4 and Y.sub.8 are driven at the same timings, respectively. As a result, the duty ratio of display becomes 2/n (n=8), two times that of the prior art.
In the LCD device as shown in FIG. 4, since the upper common drive circuit 2U and the lower common drive circuit 2L operate simultaneously in the same manner, one drive circuit can serve as them. Or, the drive section of the display panel 1w may be given as shown in FIG. 5.
Referring to FIG. 5, construction of the common electrodes Y and segment electrodes X and that of the upper and lower segment drive circuits 3U, 3L are completely the same as in the case of FIG. 4; however, the upper common electrodes Y.sub.1 -Y.sub.4 and the lower common electrodes Y.sub.5 -Y.sub.8 are connected to one common drive circuit 2D in parallel and adapted to be driven simultaneously by the same common drive circuit 2D. In this case, also, the duty ratio of display two times that of the prior art can be obtained as in the case of FIG. 4.
The display panel drive method with an LCD device such as shown in FIG. 4 or FIG. 5 is called the electrode-division method or the two-screen method, where the resulting display duty ratio becomes two times that of the prior art, as described above. In more detail, with 400 common electrodes, such a display panel drive method as shown in FIG. 1 would involve a display duty ratio of 1/400 while such a display panel drive method as shown in FIG. 4 or FIG. 5 would be improved in the ratio to 1/200, the contrast being enhanced.
However, when the LCD device as shown in FIG. 4 or FIG. 5 is used for the display-integrated type tablet device, there will arise a problem: that is, to detect coordinates of the tip of the detection pen by the above-mentioned display panel drive method, if the upper half 1wU and the lower half 1wL of the display panel 1w are simultaneously scanned in the scan method as in FIG. 1, it will be impossible to detect the position.
As an example, since point P.sub.1 represented by the symbol + in the upper half 1wU and point P.sub.2 represented by the symbol + in the lower half 1wL in FIG. 5 will have the same voltage signal induced to the detection pen at the utterly same timing, it is impossible to determine which position the detection pen designates. The case is the same with the LCD device shown in FIG. 4, in which case a detection position will exist at two points, so that the device will no longer function as a tablet.